In recent years, an integration level in an integrated circuit has greatly increased, which has been accompanied by stricter required conditions imposed on a manufacturing precision such as flatness or smoothness of a mirror-polished wafer surface. In addition, in order to achieve an integrated circuit higher in performance, reliability and product yield, not only a higher mechanical precision, but also better electric characteristics have been required. Especially, an SOI wafer, which is an ideal dielectric isolation substrate, has been used in applications to high frequency and high-speed devices mainly related to mobile communication equipment and medical equipment and further great increase in demand therefor is expected in the future.
An SOI wafer 50, as shown in FIG. 6, has a structure in which an SOI layer 52 (also referred to as a semiconductor layer or an active layer) for forming an element such as a single crystal silicon layer is formed on an insulating layer 54 (also referred to as a buried oxide (BOX) film layer or simply an oxide film layer) such as a silicon oxide film. The insulating layer 54 is formed on a support substrate 56 (also referred to as a substrate layer) and the SOI wafer 50 has a structure in which the insulating layer 54 and the SOI layer 52 are sequentially formed on the support substrate 56.
As conventional manufacturing methods for an SOI wafer 50 having the SOI structure in which the SOI layer 52 and the support substrate 56 are made of, for example, silicon and the insulating layer 54 is made of, for example, a silicon oxide film, there are exemplified an SIMOX (Separation by Implanted Oxygen) method in which oxygen ions are implanted into a silicon single crystal at a high concentration and thereafter the single crystal is subjected to heat treatment at a high temperature to form an oxide film thereon; and a bonding method (an adhering method) in which two mirror-polished wafers are bonded with each other with an oxide film interposed therebetween without the use of an adhesive, followed by processing one of the bonded wafers into a thin film.
Since the SIMOX method can controllably determine a film thickness of an active layer portion (an SOI layer) 52 to serve as a device active region by an acceleration voltage in oxygen ion implantation, there is an advantage that a thin active layer high in film thickness uniformity can be easily obtained, whereas there have remained many issues of reliability of a buried oxide film (an insulating layer) 54, crystallinity in an active layer 52, and others.
On the other hand, a wafer bonding method is carried out in such a way that an oxide film (insulating layer) 54 is formed on at least one of two single crystal silicon mirror-polished wafers, then both wafers are adhered with each other without using an adhesive, then the adhered wafers are subjected to heat treatment (usually at a temperature in the range of 1100° C. to 1200° C.) to strengthen bonding therebetween and thereafter one of the wafers is thinned into a thin film by grinding or wet etching, followed by mirror-polishing the surface of the thin film so as to obtain an SOI layer 52; which leads to advantages that reliability of the buried oxide film (an insulating layer) 54 is high and crystallinity of the SOI layer is also good. However, the thus adhered SOI wafer 50 is subjected to mechanical processing such as grinding or polishing into a thin film, and hence the obtained SOI layer 52 have limitations in its film thickness and uniformity.
As a method for manufacturing an SOI wafer, it has very recently started to pay attention to a method for manufacturing an SOI wafer by bonding an ion implanted wafer to another wafer and delaminating the wafer therefrom. This method is also referred to as an ion implantation delamination method, which is such a technique that as shown in FIG. 7, two silicon wafers are prepared; an oxide film (an insulating layer) is formed on at least one silicon wafer; hydrogen ions or rare gas ions are implanted onto an upper surface of the one silicon wafer; a micro-bubble layer (an enclosed layer) is formed in the interior of the one wafer, the surface onto which the ions are implanted is contacted and adhered with the other silicon wafer through the oxide film interposed therebetween; thereafter by applying heat treatment to the adhered wafers, a part of the one wafer is separated with the micro-bubble layer as a cleavage plane for the rest of the one wafer to become a thin film; and heat treatment is further applied to the rest of the adhered wafers to strongly bond the wafers, thereby an SOI wafer being obtained (see JP-A No. 5-211128). And according to this method, the cleavage plane is a good mirror-polished surface and the SOI wafer 50 high in uniformity of film thickness of the SOI layer 52 can be obtained with relative ease.
In FIG. 7, further detailed description will be given of the ion implantation delamination method showing one example of a set of main steps thereof There are prepared two starting wafers, that is, a base wafer 56a serving as a support substrate 56 and a bond wafer 52a from which an SOI layer 52 is formed [FIG. 7(a), step 100]. As these wafers, for example, mirror-polished silicon single crystal wafers are used.
An oxide film 54a serving as a buried oxide film (an insulating layer) at a later step is formed on a surface of the bond wafer 52a [FIG. 7(b), step 102]. This step is carried out as follows. For execution of this step, for example, thermal oxidation is applied on the bond wafer 52a of a silicon single crystal wafer to form a silicon oxide film on the bond wafer 52a. Incidentally, the formation of the oxide film may be performed on the surface of the base wafer 56a, not on the surface of the bond wafer 52a. In the illustrated embodiment, the exemplary case where the oxide film 54a is formed on the bond wafer 52a side will be explained.
Then, hydrogen ions are implanted into the bond wafer 52a through the oxide film 54a to form a micro-bubble layer (an enclosed layer) 58 [FIG. 7(c), step 104].
Thereafter, chemical cleaning may be carried out using a H2SO4—H2O2 mixed solution or the like (step 105). The H2SO4—H2O2 mixed solution has been known in a field of wet cleaning with an abbreviation of SPM (Sulfuric acid-Hydrogen Peroxide Mixture) and is a cleaning solution for removal of organic contaminants.
Then, the bond wafer 52a in which the micro-bubble layer (the enclosed layer) 58 is formed is brought into close contact with the base wafer 56a at room temperature through the oxide film on the surface of the bond wafer 52a onto which the ion implantation has been performed [FIG. 7(d), step 106].
Then, by applying heat treatment (delaminating heat treatment) at a temperature of 500° C. or higher, a part of the bond wafer 52a is delaminated at the enclosed layer 58 and the rest of the bond wafer 52a stands in the form of a thin film [FIG. 7(e), step 108]. Next, by applying bonding heat treatment [FIG. 7(f), step 110], the wafer bond 52a in the form of the thin film and the base wafer 56a are strongly bonded with each other through oxide film 54a interposed therebetween, whereby a wafer 50 having an SOI structure is manufactured.
The SOI wafer 50 manufactured using the adhering method has, at this stage, a sectional structure in which the insulating film (layer) 54 and the SOI layer 52 are separately and sequentially laminated on one main surface of the support substrate 56.
Also, as shown in FIG. 6, the insulating layer 54 and the SOI layer 52 are generally smaller in diameter than the support substrate 56 by a value of the order of several mm, usually 3 mm.
Wafers made of, for example, silicon to be used as starting wafers of the SOI wafers 50 are generally manufactured by the following process. The wafer manufacturing process includes: a slicing step of slicing a single crystal rod (ingot) produced with a single crystal producing apparatus to obtain thin disk-like wafers; a chamfering step of chamfering a peripheral edge portion of the wafer obtained in the slicing step in order to prevent cracking or chipping of the wafer; a lapping step of flattening the chamfered wafer; an etching step of removing processing deformation remaining on a surface of the chamfered and lapped wafer; a primary mirror-polishing step of stock removal polishing a surface of the etched wafer by bringing a polishing cloth into contact with the surface; a final mirror-polishing step of final mirror-polishing the surface of the primary mirror-polished wafer; and a final cleaning step of cleaning a final mirror-polished wafer to remove a polishing agent or foreign matter attached to the wafer. The above-described process shows basic steps thereof, and other steps such as a donor killer heat treatment step may be added, or the same step may be repeated several times or the step sequence may be changed.
There has been a problem of reduction in device yield in manufacturing devices using SOI wafers. As a result of serious investigation into a cause for the problem, it has been considered that defects called voids are generated in an SOI layer and an oxide film, which leads to a reduction in a device yield.
The void 70, as shown in FIG. 4, is a hole in the SOI layer or the insulating layer.